[UrJTAG-dev] automatically generated interconnection test

[Marco Behr]

Hello,

Are there any activities regarding an automatically generated interconnection
test (for finding shorts/opens in a circuit) which uses UrJtag?

I am using a commercial tool (Goepel electronics) for boundary scan tests in
the company. Then I began looking for a non-commercial / open source tool
which can do the same (with an low-cost hardware platform) so everyone at home
can use it also. Soon I found UrJtag and OpenOCD as two possible platforms but
neither one has a working implementation of this kind of test.

In fact, UrJtag seems more convenient for adding such a function:
- a working BSDL subsystem exists
- a signal structure exists with commands for driving and testing digital
values which can be extended by attributes defining the testability of these
nets (Are other drivers connected to these nets? Are pull-resistors connected?
...)

I would like to know if there is interest in adding such a function or if
there are already some ideas on how this should look like? Are there any
solutions on the internet which I haven't found looking for it?

I have some experience with the commercial solutions and I am ready to spend
some time in implementing a kind of interconnection test. Maybe I will be
doing this as part of my master thesis, but the main goal should be to make
this functionality available to the public.

marco

[Tim Ansell]

Hi Marco,

Firstly, I'm not a urjtag developer - I've just used it a bunch.

I haven't seen any activity on this list in the past 6 months I have been
on it compared to the OpenOCD list which seems to be significantly more
active. Hence, I'd personally suggest trying to add the functionality to
OpenOCD even if it is harder.

Tim 'mithro' Ansell

Post by Marco Behr
Hello,
Are there any activities regarding an automatically generated
interconnection
test (for finding shorts/opens in a circuit) which uses UrJtag?
I am using a commercial tool (Goepel electronics) for boundary scan tests in
the company. Then I began looking for a non-commercial / open source tool
which can do the same (with an low-cost hardware platform) so everyone at home
can use it also. Soon I found UrJtag and OpenOCD as two possible platforms but
neither one has a working implementation of this kind of test.
- a working BSDL subsystem exists
- a signal structure exists with commands for driving and testing digital
values which can be extended by attributes defining the testability of these
nets (Are other drivers connected to these nets? Are pull-resistors connected?
...)
I would like to know if there is interest in adding such a function or if
there are already some ideas on how this should look like? Are there any
solutions on the internet which I haven't found looking for it?
I have some experience with the commercial solutions and I am ready to spend
some time in implementing a kind of interconnection test. Maybe I will be
doing this as part of my master thesis, but the main goal should be to make
this functionality available to the public.
marco
------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785471&iu=/4140
_______________________________________________
UrJTAG-development mailing list
https://lists.sourceforge.net/lists/listinfo/urjtag-development

[Johann Klammer]

Post by Marco Behr
Hello,
Are there any activities regarding an automatically generated interconnection
test (for finding shorts/opens in a circuit) which uses UrJtag?
I am using a commercial tool (Goepel electronics) for boundary scan tests in
the company. Then I began looking for a non-commercial / open source tool
which can do the same (with an low-cost hardware platform) so everyone at home
can use it also. Soon I found UrJtag and OpenOCD as two possible platforms but
neither one has a working implementation of this kind of test.
- a working BSDL subsystem exists
- a signal structure exists with commands for driving and testing digital
values which can be extended by attributes defining the testability of these
nets (Are other drivers connected to these nets? Are pull-resistors connected?
...)
I would like to know if there is interest in adding such a function or if
there are already some ideas on how this should look like? Are there any
solutions on the internet which I haven't found looking for it?
I have some experience with the commercial solutions and I am ready to spend
some time in implementing a kind of interconnection test. Maybe I will be
doing this as part of my master thesis, but the main goal should be to make
this functionality available to the public.
marco
------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785471&iu=/4140

I have used urjtags .svf replay capability to do test vector injection in a CPLD.
the .svf file was generated by a program. You may be able to modify it to your needs.
The code is not device-specific, so it'll work if you have a bsdl file.

<https://github.com/klammerj/vec2svf>

Things to look out for:

urjtag does not handle multiple device chains correctly, so you'll have to modify
their .svf stuff if you want it to work(vec2svf can't handle it either).

vec2svf acitvely(!) drives values onto the device I/Os then reads out the
device internal values for I/O and port-enables. This is likely not what you
want for your use-case(other stuff may be connected/destroyed).
You'll likely have to modify that.



------------------------------------------------------------------------------

[Markus Schneider]

Hello,

long time ago, I have made a urjtag extension for the Goepel Boundary
Scan Coach, a Boundary Scan demo board.
I have worked in the past also with Goepel tools and had the idea to
create a pattern generator for
a interconnection or memory test.
But it was just a idea, and the lack of a powerful free available JTAG
Bus master and the complexity of this task
stops this attempt early.
If you have ideas for pattern generator algorithms it would be
interesting to revive the urjtag project.

Markus

Post by Johann Klammer

Post by Marco Behr
Hello,
Are there any activities regarding an automatically generated interconnection
test (for finding shorts/opens in a circuit) which uses UrJtag?
I am using a commercial tool (Goepel electronics) for boundary scan tests in
the company. Then I began looking for a non-commercial / open source tool
which can do the same (with an low-cost hardware platform) so everyone at home
can use it also. Soon I found UrJtag and OpenOCD as two possible platforms but
neither one has a working implementation of this kind of test.
- a working BSDL subsystem exists
- a signal structure exists with commands for driving and testing digital
values which can be extended by attributes defining the testability of these
nets (Are other drivers connected to these nets? Are pull-resistors connected?
...)
I would like to know if there is interest in adding such a function or if
there are already some ideas on how this should look like? Are there any
solutions on the internet which I haven't found looking for it?
I have some experience with the commercial solutions and I am ready to spend
some time in implementing a kind of interconnection test. Maybe I will be
doing this as part of my master thesis, but the main goal should be to make
this functionality available to the public.
marco
------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785471&iu=/4140

I have used urjtags .svf replay capability to do test vector injection in a CPLD.
the .svf file was generated by a program. You may be able to modify it to your needs.
The code is not device-specific, so it'll work if you have a bsdl file.
<https://github.com/klammerj/vec2svf>
urjtag does not handle multiple device chains correctly, so you'll have to modify
their .svf stuff if you want it to work(vec2svf can't handle it either).
vec2svf acitvely(!) drives values onto the device I/Os then reads out the
device internal values for I/O and port-enables. This is likely not what you
want for your use-case(other stuff may be connected/destroyed).
You'll likely have to modify that.
------------------------------------------------------------------------------
_______________________________________________
UrJTAG-development mailing list
https://lists.sourceforge.net/lists/listinfo/urjtag-development

------------------------------------------------------------------------------

[Marco Behr]

Hello Paul,

thanks for your quick reply. I was not available a few days so I couldn't
answer earlier.

Hello Marco,
Speaking as an OpenOCD "fan" here, so please excuse my bias and
writing off-list :)

Post by Marco Behr
I am using a commercial tool (Goepel electronics) for boundary scan tests
in the company. Then I began looking for a non-commercial / open source
tool which can do the same (with an low-cost hardware platform) so
everyone at home can use it also. Soon I found UrJtag and OpenOCD as two
possible platforms but neither one has a working implementation of this
kind of test.

Yes, UrJTAG has BSDL parser integrated but I'm not sure what real
advantage that gives. When one is testing something manually he can
easily interpret BSDL himself and I wrote some additional OpenOCD
scripts to be able to do boundary scan, see here[1].

The BSDL parser is good for quickly collecting ALL the information in the BSDL
file. For an manually written test, it works fine when you only look for a
single ports BScan cells and then write test pattern to them.

But what I want to do is to define attributes for all reachable ports on the
chip so the software can automatically generate big test vectors (e.g. using
the counting pattern algorithm described by Kenneth P. Parker in his patent EP
0543506 B1) to detect shorts / opens between many nets.

But when it comes to automating it, my guess is that the most
straightforward way would be to write an SVF file generator. With
OpenOCD you can playback SVF with any kind of adapter, be it cheap
J-Link clone, FTDI-based device or even just about any Single Board
Computer (and for RaspberryPi there's a dedicated fast driver).

Yes, SVF might be an option and both OpenOCD and UrJtag are able to play them.
(And I think a few more software platforms can do this). But neither one can
play SVF files on multiple devices. And furthermore tests on multiple JTAG
chains simultaneously are absolutely not possible. So I think SVF might only
solve a part of the problem.

There's also an OpenOCD enthusiast that has just shared a Python
parser for BSDL[2]. I think if you take something like that and
generate an SVF file from Python, playing it back with OpenOCD would
be a nice way to test your hardware.

I had a look at this Python based parser - unfortunately I am completely new
to Python. Although this one looks interesting and I will consider using it
too.

Please feel free to share your thoughts and needs on the openocd-devel
mailing list.

As I already said, I am thinking also about implementing these functions into
OpenOCD instead of UrJtag.
+ there is much more activity at the OpenOCD project than at UrJtag
+ the Jim-Tcl implementation is also pretty useful
- the main object of OOCD is debugging of software - not testing / debugging
of circuits
- OpenOCD doesn't allow multiple devices in a chain to be active (not
bypassed)

Good luck,
And happy hacking :)
[1] https://sourceforge.net/p/openocd/mailman/message/31069985/
[2] https://github.com/cyrozap/python-bsdl-parser

Thank you for your ideas - I will share this also on the OpenOCD mailing list



------------------------------------------------------------------------------

[Paul Fertser]

This post might be inappropriate. Click to display it.

[Michael Walle]

Post by Marco Behr
As I already said, I am thinking also about implementing these
functions into
OpenOCD instead of UrJtag.
+ there is much more activity at the OpenOCD project than at UrJtag
+ the Jim-Tcl implementation is also pretty useful
- the main object of OOCD is debugging of software - not testing / debugging
of circuits
- OpenOCD doesn't allow multiple devices in a chain to be active (not
bypassed)

Yeah, its sad to see urjtag slowly dying. Because actually, as you said,
the interconnection test hasn't anything to do with CPU debugging (which
is OpenOCD for). Actually I'm surprised OpenOCD has a SVF player
integrated, because the main use is flashing CPLDs, isn't it? And IMHO
urjtag has the better codebase, at least this was the case some years
ago. This is just my opinion.

-michael