[UrJTAG-dev] Lattice ECP3 support - bsdl2jtag 'unsupported construct' with git head

[Chris Shucksmith]

Hello All,

I am trying to add support for a Lattice ECP3 35EA FPGA, as used on
the Lattice Versa development board. I am trying to write to the SPI
Flash which is reached 'through' the FPGA (schematics at
http://www.latticesemi.com/documents/EB62.pdf ).

The board uses a FT2232 chip with JTAG bus on interface 0, initially
the FPGA was recognised as an unknown lattice part. I added an entry
to data/lattice/PARTS to recognise the device as "lfe3-35ea".

There is a public BSDL model for the device published by Lattice
http://www.latticesemi.com/documents/lfe3_35ea_fpbga484.bsm When I
try to translate this into urjtag format, the lexer dies on line
#1066:

$ /usr/local/bin/bsdl2jtag lfe3_35ea_fpbga484.bsm lfe3_35ea
error: -E- error: Line 1066, Unsupported BSDL construct found.
error: -E- error: BSDL stage reported errors, aborting.
error: bsdl subsystem: Parser error, see log for details

The BSDL file comments suggest it conforms to "IEEE Standard
1149.1-2001" but the lexer source (in urjtag/bsdl/bsdl_flex.l )
suggests compatibility with 1149.1 "1990" (!). However I see that
someone has managed to put together a specification for lfec2-12e
lattice part so this must be possible - is there a secret or was it
translated by hand?

The errors seem to be caused by entries grouped under
"DIFFERENTIAL_CURRENT" but I don't know enough yet about the tools and
format to debug further. I don't care too much about being able to
drive pins for board testing, only looking to implement flash writes.

I would be able to hook up a logic probe on either the SPI flash or
the JTAG bus to record the commands issued by the vendor tooling if
that's required to figure out the write thru SPI commands.

Any help at this stage would be appreciated.

Chris

$ /usr/local/bin/jtag

UrJTAG 0.10 #2026
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.

warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable FT2232 vid=0x0403 pid=0x6010 interface=0
Connected to libftdi driver.
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00000001000000010010000001000011 (0x01012043)
Manufacturer: Lattice Semiconductors (0x043)
Part(0): LFE3_35EA (0x1012)
Stepping: 0
Filename: /usr/local/share/urjtag/lattice/lfe3-35ea/lfe3-35ea
error: system error: No such file or directory Cannot open file
'/usr/local/share/urjtag/lattice/lfe3-35ea/lfe3-35ea' to parse
jtag> quit

[Chris Shucksmith]

Hi,
Trimming out the PORT_GROUPING attribute allowed the rest of the
Lattice BSDL to be parsed. I have a patch that adds the device to the
database (not sure if you pull commits from Github or not) here:
https://github.com/shuckc/urjtag/commit/a131efaef0dca84a5b8a7860d3158e13f4493f62

Programming the chip using .SVF files output from the vendor tool
chain worked, as did reading the BSR.

My interest was to build some automated hardware regression tests
after programming, so I added a function 'get_dr_out_boundary_dict' to
the Python bindings. This returns the contents of the BSR register as
a dictionary, keyed by the pin names - sample below. Commit is:
https://github.com/shuckc/urjtag/commit/12086b4d2b76ad52c792b33975e92bb8756a42f7

Would be happy to rework as required to get either upstream if you are willing.

Chris

$ ./jtagRead.py
Connected to libftdi driver.
IR length: 8
Chain length: 1
Device Id: 00000001000000010010000001000011 (0x01012043)
Manufacturer: Lattice Semiconductors (0x043)
Part(0): LFE3_35EA (0x1012)
Stepping: 0
Filename: /usr/share/urjtag/lattice/lfe3-35ea/lfe3_35ea_fpbga484

LED0 DL UP 1 (PR66A)
LED1 L0 1 (PR66B)
LED2 Poll 1 (PR68A)
LED3 PLL 1 (PR68B)
LED4 0 (PR69A)
LED5 0 (PR69B)
LED6 0 (PR71A)
LED7 0 (PR71B)

$ cat jtagRead.py
#!/usr/bin/python
import urjtag

urc = urjtag.chain()
urc.cable("FT2232", "vid=0x0403", "pid=0x6010", "interface=0")
urc.tap_detect()

# setup chain to part0, sample pins
urc.part(0)
urc.set_instruction('SAMPLE/PRELOAD')
urc.shift_ir()

# shift data through
urc.shift_dr()
outval = urc.get_dr_out_boundary_dict()

print
for (x,(port,fn)) in enumerate([
('PR66A','DL UP'),
('PR66B','L0'),
('PR68A','Poll'),
('PR68B','PLL'),
('PR69A',''),
('PR69B',''),
('PR71A',''),
('PR71B','')
]):
print "LED%d %8s %2d (%s)" % (x, fn, 1-outval[port],port)

[Mike Frysinger]

Post by Chris Shucksmith
Trimming out the PORT_GROUPING attribute allowed the rest of the
Lattice BSDL to be parsed. I have a patch that adds the device to the
database (not sure if you pull commits from Github or not)

currently, we do not. please use `git send-email` to post to the list.
-mike